Attention
This documentation is a work in progress. Expect to see errors and unfinished things.
ph_acc
Description
Phase accumulator, to act as basis for DDS (direct digital synthesizer).
Tuned to allow 32-bit control, divided 20-bit high and 12-bit low,
which gets merged to 32-bit binary when modulo is zero.
But also supports non-binary frequencies: see the modulo input port.
Pinout
Ports
Signal |
Direction |
Description |
|---|---|---|
clk |
Input |
Rising edge clock input; all logic is synchronous in this domain |
reset |
Input |
Active high, synchronous with clk |
en |
Input |
Enable |
phase_acc[18:0] |
Output |
Output phase word |
phase_step_h[19:0] |
Input |
High order (coarse, binary) phase step |
phase_step_l[11:0] |
Input |
Low order (fine, possibly non-binary) phase step |
modulo[11:0] |
Input |
Encoding of non-binary modulus; 0 means binary |
Implementation and use
The portable Verilog implementation can be found in ph_acc Source File