Attention

This documentation is a work in progress. Expect to see errors and unfinished things.

mon_chans

Description

Pinout

Parameters

Table 102 mon_chans_param_table

Name	Min	Max	Default	Description
NCHAN	?	?	1
DWI	?	?	16	data width
RWI	?	?	28	result width
DWLO	?	?	18	Local Oscillator data width
DAVR	?	?	3

Ports

Table 103 mon_chans_port_table

Signal	Direction	Description
clk	Input	timespec 8.4 ns
adc[NCHAN*DWI-1:0]	Input	possibly muxed
mlo[NCHAN*DWLO-1:0]	Input
samp	Input
s_in[RWI-1:0]	Input
s_out[RWI-1:0]	Output
g_in	Input
g_out	Output
reset	Input

Implementation and use

The portable Verilog implementation can be found in mon_chans Source File