Attention
This documentation is a work in progress. Expect to see errors and unfinished things.
serializer_multichannel
Description
Pinout
Parameters
Name |
Min |
Max |
Default |
Description |
|---|---|---|---|---|
n_chan |
? |
? |
8 |
Number of channels to serialize |
dw |
? |
? |
16 |
|
l_to_r |
? |
? |
1 |
l_to_r=1: Channel shifting starts with CH0 (default) |
Ports
Signal |
Direction |
Description |
|---|---|---|
clk |
Input |
|
sample_in |
Input |
Sampling signal which determines when to push inputs to belt |
data_in[n_chan*dw-1:0] |
Input |
Flattened array of unprocessed data streams |
gate_out |
Output |
|
stream_out[dw-1:0] |
Output |
Serialized stream of channels. Default order is CH0 first (l_to_r=1) |
Implementation and use
The portable Verilog implementation can be found in serializer_multichannel Source File
Timing Diagram
A GTKWave-generated timing diagram is shown below:
