Attention

This documentation is a work in progress. Expect to see errors and unfinished things.

tt800

Description

A synthesizable Verilog program for TT800
Adapted from Twisted GFSR Generators II
Makoto Matsumoto and Yoshiharu Kurita
December 2, 1992
http://www.math.sci.hiroshima-u.ac.jp/~m-mat/eindex.html

Pinout

Ports

Table 140 tt800_port_table
Signal	Direction	Description
clk	Input	timespec 3.0 ns
en	Input
init	Input
initv[31:0]	Input
y[31:0]	Output

Implementation and use

The portable Verilog implementation can be found in tt800 Source File

Timing Diagram

A GTKWave-generated timing diagram is shown below: