Attention

This documentation is a work in progress. Expect to see errors and unfinished things.

rr_arb

Pinout

Parameters

Table 123 rr_arb_param_table

Name	Min	Max	Default	Description
NREQ	?	?	2

Ports

Table 124 rr_arb_port_table

Signal	Direction	Description
clk	Input
req_bus[NREQ-1:0]	Input
grant_bus[NREQ-1:0]	Output
reqs[NREQ-1:0]	Input
base[NREQ-1:0]	Input

Implementation and use

The portable Verilog implementation can be found in rr_arb Source File