Attention

This documentation is a work in progress. Expect to see errors and unfinished things.

iq_intrp4

Description

Pull apart and interpolate a four-way interpolated IQ stream

into its individual components

Pinout

Ports

Table 82 iq_intrp4_port_table

Signal	Direction	Description
clk	Input
sync	Input
in[21:0]	Input
out1[17:0]	Output
out2[17:0]	Output
out3[17:0]	Output
out4[17:0]	Output

Implementation and use

The portable Verilog implementation can be found in iq_intrp4 Source File